Design-for-Test (DFT) is used throughout the semiconductor industry for digital circuits, using a structural test paradigm. Rather than determine overall functionality of a circuit, structural test determines whether the circuit has been assembled correctly from low-level building blocks as specified in a structural netlist. For example, a DFT test may determine whether all specified logic gates are present, operating correctly, and connected correctly. If the netlist is correct, and structural testing confirms the correct assembly of the circuit elements, then the circuit should function correctly.
IEEE std. 1149.1/4/6 and IEEE std. 1500 are standard serial interfaces for DFT testing. DFT testing requires a long testing time, as large numbers of individual components and nodes are checked. An open circuit in a serial chain will stop further testing.